U.S. Pat. No. 6,789,222 (the '222 patent) teaches complete test pattern generation methods for combinational circuits, and describes a robust set of fault-propagation rules appropriate for use in sequential test pattern generation. The methods of the '222 patent find all test patterns for all detectable faults during a single pass through a circuit-level sorted description of a combinational circuit.
A sequential circuit can be represented as a combinational part and a separate feedback storage part (prior art FIG. 1). The sequential circuit can be analyzed as an iterative array of the combinational parts, each part containing a copy of the fault (prior art FIG. 2; see for example, K-T Cheng, “Tutorial and Survey Paper: Gate-Level Test Generation for Sequential Circuits,” ACM Trans. Design Automation of Electronic Sys. Vol. 1, No. 4, October 1996, Pages 405-442).
The teachings of the '222 patent can be applied to such an iterative array for generating test pattern sequences for sequentially detectable faults. This approach is taken in U.S. Pat. No. 7,231,571 (the '571 patent), and in co-pending U.S. patent application Ser. No. 11/893,683 (the '683 patent application). Both teach single-pass methods for sequential test pattern generation. However, in each, the appearance of a fault at a circuit primary output line is not a reliable indication of the existence of a valid test sequence. As a result, potential test sequences must be independently validated.
What is needed is a deterministic test pattern generator for sequential circuits that finds test pattern sequences for sequentially detectable faults during a single pass through an iterative array representation of a sequential circuit, without a need for independent validation.
The test pattern generator should use data structures having size bounded by the number of state and input variables required during an initial time-frame.
It should be unnecessary to predict a maximum number of time-frames that may be required, instead simply proceeding from time-frame to time-frame until a test is found or until the process is otherwise terminated.
Finally, for all faults during all subsequent time-frames, the test pattern generator should permit reuse of path-enabling functions created and used during an initial time-frame.